1. Field of the Invention
This invention relates to bistable regenerative solid state memory cells, and particularly to such cells where redundant elements are employed to protect the logic state of the cell against upset due to radiation.
2. Related Art
FIG. 1 shows a basic known solid state bistable regenerative memory cell. Random access memories (RAMs) use a matrix of such cells, each adapted to be uniquely written into or read.
Radiation, such as alpha particles or cosmic rays, cause transients in memory cells as they penetrate into the cell. These transients can trigger the bistable circuit by changing the current or voltage at a transistor node thereby causing the cell to switch logic states.
In bipolar memory cells, the causes of such radiation-induced upset are primarily (1) collector nodes of OFF transistors can short to ground, and (2) base nodes of OFF transistors can short to collector nodes turning OFF transistors ON. The first mechanism is the dominant cause of single event upset (SEU) in cosmic ray environments. This mechanism, with small variations in charge collection volume and circuit upset threshold, is also found in other semiconductor technologies such as N-channel metal oxide semiconductor/silicon (NMOS/Si) and complementary metal oxide semiconductor/silicon (CMOS/Si).
The second upset mechanism is found only in bipolar devices. Here a parasitic current path is formed within the device itself rather than between the device and the substrate. The second upset mechanism involves a smaller amount of upset charge which can still cause upset at high LET values (LET denotes linear energy transfer, which is the amount of energy deposited in the semiconductor by the radiation). It is estimated that if the first upset mechanism is eliminated completely, then the second upset mechanism will still limit the error rate to about 1E-7 (i.e., 1.times.10.sup.-7) errors per bit-day.
Various techniques have been proposed for hardening bipolar circuits to SEU. However, all of these techniques address only the first type of upset mechanism listed above. They propose to either remove the collector from electrical contact with the substrate or reduce the charge injected into the collector node. The most effective of these other techniques--dielectric isolation--completely isolates the collector from the substrate.
Eliminating SEU-induced collector-to-base shorts is much more difficult. Pulse rise time can be used to discriminate SEU currents from normal device currents. This forms the basis for CMOS hardening by means of cross-coupled resistors or extra capacitance. But this technique degrades the speed of bipolar circuits so much that they lose their competitive advantage against CMOS.
Photocurrent compensation techniques are also ineffective against the second form of SEU because the upset current varies with the direction of ion incidence. Geometric effects practically rule out the location of a second charge collection region which can produce an equal but oppositely directed photocurrent from the same ion path. Finally, circumvention techniques are almost totally ineffective because of the difficulty of sensing a time-random ion event at every transistor node and recovering fast enough (e.g., 0.2 ns) to prevent an upset.
A bit error rate of 1E-10 error/bit-day is being sought for memory elements in a cosmic ray environment. This corresponds to approximately three years without an error for a one megaword memory. Only one technology complementary metal oxide semiconductor/silicon on sapphire (CMOS/SOS) can meet this goal at present, but CMOS/bulk silicon is constantly being improved and may be able to meet this goal in the near future. No bipolar technology, however, can approach this goal.
Ever more stringent error/bit-day rates are highly desirable with the enormous increase in memory capacity being projected for general purpose computers. In a general purpose computer an error in the register bit or memory bit can be retained and used in a number of calculations. If the bit is a critical value, the consequences of even one error can be disastrous.
It is thus highly desirable to have a memory cell which is extremely resistant to both types of SEU. It is further highly desirable to have such a cell which is adaptable to either unipolar or bipolar transistor circuits.